View AD8251-EVALZ_9000185.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

10 mhz, 20 v/s, g = 1, 2, 4, 8 i cmos programmable gain instrumentation amplifier ad8251 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2010 analog devices, inc. all rights reserved. features small package: 10-lead msop programmable gains: 1, 2, 4, 8 digital or pin-programmable gain setting wide supply: 5 v to 15 v excellent dc performance high cmrr: 98 db (minimum), g = 8 low gain drift: 10 ppm/c (maximum) low offset drift: 1.8 v/c (maximum), g = 8 excellent ac performance fast settling time: 785 ns to 0.001% (maximum) high slew rate: 20 v/s (minimum) low distortion: ?110 db thd at 1 khz, 10 v swing high cmrr over frequency: 80 db to 50 khz (minimum) low noise: 18 nv/hz, g = 8 (maximum) low power: 4.1 ma applications data acquisition biomedical analysis test and measurement general description the ad8251 is an instrumentation amplifier with digitally programmable gains that has g input impedance, low output noise, and low distortion, making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters (adcs). it has a high bandwidth of 10 mhz, low thd of ?110 db, and fast settling time of 785 ns (maximum) to 0.001%. offset drift and gain drift are guaranteed to 1.8 v/c and 10 ppm/c, respectively, for g = 8. in addition to its wide input common voltage range, it boasts a high common-mode rejection of 80 db at g = 1 from dc to 50 khz. the combination of precision dc performance coupled with high speed capabilities makes the ad8251 an excellent candidate for data acquisition. furthermore, this monolithic solution simplifies design and manufacturing and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers. the ad8251 user interface consists of a parallel port that allows users to set the gain in one of two ways (see figure 1). a 2-bit word sent via a bus can be latched using the wr input. an alternative is to use the transparent gain mode where the state of the logic levels at the gain port determines the gain. functional block diagram a1 a0 dgnd wr ad8251 +v s ?v s ref out +in logic ?in 1 10 8 3 7 4 5 6 2 9 06287-001 figure 1. 25 ?10 1k 100m 06287-002 frequency (hz) gain (db) 10k 100k 1m 10m 20 15 10 5 0 ?5 g = 1 g = 2 g = 4 g = 8 figure 2. gain vs. frequency table 1. instrumentation amplifiers by category general purpose zero drift mil grade low power high speed pga ad8220 1 ad8231 1 ad620 ad627 1 ad8250 ad8221 ad8553 1 ad621 ad623 1 ad8251 ad8222 ad8555 1 ad524 ad8223 1 ad8253 ad8224 1 ad8556 1 ad526 ad8228 ad8557 1 ad624 1 rail-to-rail output. the ad8251 is available in a 10-lead msop package and is specified over the ?40c to +85c temperature range, making it an excellent solution for applications where size and packing density are important considerations.
ad8251* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ad8251 evaluation board documentation application notes ? an-1401: instrumentation amplifier common-mode range: the diamond plot data sheet ? ad8251: 10 mhz, 20 v/s, g = 1, 2, 4, 8 i cmos programmable gain instrumentation amplifier data sheet technical books ? a designer's guide to instrumentation amplifiers, 3rd edition, 2006 user guides ? ug-925: evaluating the ad8251 10 mhz, 20 v/s, g = 1, 2, 4, 8 i icmos programmable gain instrumentation amplifier tools and simulations ? ad8251 spice macro model reference materials technical articles ? auto-zero amplifiers ? high-performance adder uses instrumentation amplifiers design resources ? ad8251 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad8251 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ad8251 rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing diagram ........................................................................... 5 absolute maximum ratings............................................................ 6 maximum power dissipation ..................................................... 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 16 gain selection ............................................................................. 16 power supply regulation and bypassing ................................ 18 input bias current return path ............................................... 18 input protection ......................................................................... 18 reference terminal .................................................................... 19 common-mode input voltage range ..................................... 19 layout .......................................................................................... 19 rf interference ........................................................................... 20 driving an adc ......................................................................... 20 applications..................................................................................... 21 differential output .................................................................... 21 setting gains with a microcontroller ...................................... 21 data acquisition......................................................................... 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 11/10rev. a to rev. b changes to voltage offset, offset rti v os , average tc parameter in table 2......................................................................... 3 updated outline dimensions ....................................................... 23 5/08rev. 0 to rev. a changes to table 1............................................................................ 1 changes to table 2.............................................................................3 changes to table 3.............................................................................6 inserted figure 17; renumbered sequentially ..............................9 inserted figure 29........................................................................... 11 changes to timing for latched gain mode section ................. 17 5/07revision 0: initial version
ad8251 rev. b | page 3 of 24 specifications +v s = 15 v, ?v s = ?15 v, v ref = 0 v @ t a = 25c, g = 1, r l = 2 k, unless otherwise noted. table 2. parameter conditions min typ max unit common-mode rejection ratio (cmrr) cmrr to 60 hz with 1 k source imbalance +in = ?in = ?10 v to +10 v g = 1 80 98 db g = 2 86 104 db g = 4 92 110 db g = 8 98 110 db cmrr to 50 khz +in = ?in = ?10 v to +10 v g = 1 80 db g = 2 84 db g = 4 86 db g = 8 86 db noise voltage noise, 1 khz, rti g = 1 40 nv/hz g = 2 27 nv/hz g = 4 22 nv/hz g = 8 18 nv/hz 0.1 hz to 10 hz, rti g = 1 2.5 v p-p g = 2 2.5 v p-p g = 4 1.8 v p-p g = 8 1.2 v p-p current noise, 1 khz 5 pa/hz current noise, 0.1 hz to 10 hz 60 pa p-p voltage offset offset rti v os g = 1, 2, 4, 8 (70 + 200/g) (200 + 600/g) v over temperature t = ?40c to +85c (90 + 300/g) (260 + 900/g) v average tc t = ?40c to +85c ( 0.6 + 1.5/g) (1.2 + 5/g) v/c offset referred to the input vs. supply (psr) v s = 5 v to 15 v (2 + 7/g) (6 + 20/g) v/v input current input bias current 5 30 na over temperature t = ?40c to +85c 40 na average tc t = ?40c to +85c 400 pa/c input offset current 5 30 na over temperature t = ?40c to +85c 30 na average tc t = ?40c to +85c 160 pa/c dynamic response small signal ?3 db bandwidth g = 1 10 mhz g = 2 10 mhz g = 4 8 mhz g = 8 2.5 mhz settling time 0.01% out = 10 v step g = 1 615 ns g = 2 460 ns g = 4 460 ns g = 8 625 ns
ad8251 rev. b | page 4 of 24 parameter conditions min typ max unit settling time 0.001% out = 10 v step g = 1 785 ns g = 2 700 ns g = 4 700 ns g = 8 770 ns slew rate g = 1 20 v/s g = 2 30 v/s g = 4 30 v/s g = 8 30 v/s total harmonic distortion + noise f = 1 khz, r l = 10 k, 10 v, g = 1, 10 hz to 22 khz band- pass filter ?110 db gain gain range g = 1, 2, 4, 8 1 8 v/v gain error out = 10 v g = 1 0.03 % g = 2, 4, 8 0.04 % gain nonlinearity out = ?10 v to +10 v g = 1 r l = 10 k, 2 k, 600 9 ppm g = 2 r l = 10 k, 2 k, 600 12 ppm g = 4 r l = 10 k, 2 k, 600 12 ppm g = 8 r l = 10 k, 2 k, 600 15 ppm gain vs. temperature all gains 3 10 ppm/c input input impedance differential 5.3||0.5 g ||pf common mode 1.25||2 g ||pf input operating voltage range v s = 5 v to 15 v ?v s + 1.5 +v s ? 1.5 v over temperature t = ?40c to +85c ?v s + 1.6 +v s ? 1.7 v output output swing ?13.5 +13.5 v over temperature t = ?40c to +85c ?13.5 +13.5 v short-circuit current 37 ma reference input r in 20 k i in +in, ?in, ref = 0 1 a voltage range ?v s +v s v gain to output 1 0.0001 v/v digital logic digital ground voltage, dgnd referred to gnd ?v s + 4.25 0 +v s ? 2.7 v digital input voltage low referred to gnd dgnd 2.1 v digital input voltage high referred to gnd 2.8 +v s v digital input current 1 a gain switching time 1 325 ns t su see figure 3 timing diagram 20 ns t hd see figure 3 timing diagram 10 ns t wr -low see figure 3 timing diagram 20 ns t wr -high see figure 3 timing diagram 40 ns
ad8251 rev. b | page 5 of 24 parameter conditions min typ max unit power supply operating range 5 15 v quiescent current, +i s 4.1 4.5 ma quiescent current, ?i s 3.7 4.5 ma over temperature t = ?40c to +85c 4.5 ma temperature range specified performance ?40 +85 c 1 add time for the output to slew and settle to calculate the total time for a gain change. timing diagram a0, a1 wr t su t hd t wr-high t wr-low 0 6287-003 figure 3. timing diagram for latched gain mode (see the timing for latched gain mode section)
ad8251 rev. b | page 6 of 24 absolute maximum ratings table 3. parameter rating supply voltage 17 v power dissipation see figure 4 output short-circuit current indefinite 1 common-mode input voltage +v s + 13 v to ?v s ? 13 v differential input voltage +v s + 13 v, ?v s ? 13 v 2 digital logic inputs v s storage temperature range ?65c to +125c operating temperature range 3 ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 140c ja (four-layer jedec standard board) 112c/w package glass transition temperature 140c 1 assumes the load is referenced to midsupply. 2 current must be kept to less than 6 ma. 3 temperature for specifie d performance is ?40c to +85c. for performance to +125c, see the typical performance characteristics section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissipation the maximum safe power dissipation in the ad8251 package is limited by the associated rise in junction temperature (t j ) on the die. the plastic encapsulating the die locally reaches the junction temperature. at approximately 140c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8251. exceeding a junction temperature of 140c for an extended period can result in changes in silicon devices, potentially causing failure. the still air thermal properties of the package and pcb ( ja ), the ambient temperature (t a ), and the total power dissipated in the package (p d ) determine the junction temperature of the die. the junction temperature is calculated as ( ) ja d a j ptt += the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). assuming the load (r l ) is referenced to midsupply, the total drive power is v s /2 i out , some of which is dissipated in the package and some in the load (v out i out ). the difference between the total drive power and the load power is the drive power dissipated in the package. p d = quiescent power + ( total drive power ? load power ) () l out l out s ss d r v r v v ivp 2 C 2 ? ? ? ? ? ? ? ? += in single-supply operation with r l referenced to ?v s , the worst case is v out = v s /2. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a four-layer jedec standard board. 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 ?40 ?20 120 100 80604020 0 maximum power dissipation (w) ambient temperature (c) 06287-004 figure 4. maximum power dissipation vs. ambient temperature esd caution
ad8251 rev. b | page 7 of 24 pin configuration and fu nction descriptions ?in dgnd ?v s a0 a1 +in ref +v s out wr ad8251 top view (not to scale) 1 2 3 4 5 10 9 8 7 6 06287-005 figure 5. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 ?in inverting input terminal. true differential input. 2 dgnd digital ground. 3 ?v s negative supply terminal. 4 a0 gain setting pin (lsb). 5 a1 gain setting pin (msb). 6 wr write enable. 7 out output terminal. 8 +v s positive supply terminal. 9 ref reference voltage terminal. 10 +in noninverting input terminal. true differential input.
ad8251 rev. b | page 8 of 24 typical performance characteristics t a = 25c, +v s = +15 v, ?v s = ?15 v, r l = 10 k, unless otherwise noted. input offset current (na) 800 400 600 200 0 500 700 300 100 30 20 10 0 06287-009 number of units ?30 ?10 ?20 cmrr (v/v) 2700 0 120 06287-006 number of units 2400 2100 1800 1500 1200 900 600 300 ?120 ?90 ?60 ?30 0 30 60 90 figure 9. typical distribution of input offset current figure 6. typical distribution of cmrr, g = 1 06287-010 90 0 1 100k frequency (hz) noise (nv/ hz) 10 100 1k 10k 80 70 60 50 40 30 20 10 g = 1 g = 2 g = 4 g = 8 input offset voltage, v osi , rti (v) 500 300 100 400 200 0 200 100 0 06287-007 number of units ?200 ?100 figure 10. voltage spectral density noise vs. frequency figure 7. typical distributi on of offset voltage, v osi 0 6287-011 1s/div 2v/div input bias current (na) 800 400 600 200 0 30 20 10 0 06287-008 number of units ?30 ?10 ?20 figure 11. 0.1 hz to 10 hz rti voltage noise, g = 1 figure 8. typical distributi on of input bias current
ad8251 rev. b | page 9 of 24 0 6287-012 1s/div 1.25v/div figure 12. 0.1 hz to 10 hz rti voltage noise, g = 8 06287-013 18 0 1 100k frequency (hz) noise (pa/ hz) 10 100 1k 10k 16 14 12 10 8 6 4 2 figure 13. current noise spectral density vs. frequency 0 6287-014 1s/div 140pa/div figure 14. 0.1 hz to 10 hz current noise 150 130 110 90 50 70 10 10 1m 06287-016 frequency (hz) psrr (db) 100 1k 10k 100k 30 g = 1 g = 8 g = 2 g = 4 figure 15. positive psrr vs. frequency, rti 150 110 130 90 70 30 10 50 10 1m 06287-017 frequency (hz) psrr (db) 100 1k 10k 100k g=1 g=2 g=4 g=8 figure 16. negative psrr vs. frequency, rti 10 9 8 7 6 5 4 3 2 1 0 0.01 1 0.1 change in offset voltage, rti (v) 10 warm-up time (minutes) 06287-117 figure 17. change in offset voltage, rti vs. warmup time
ad8251 rev. b | page 10 of 24 20 ?10 ?60 140 06287-019 temperature (oc) input bias current and offset current (na) 15 10 5 0 ?5 ?40 ?20 0 20 40 60 80 120 100 i b ? i os i b + figure 18. input bias current and offset current vs. temperature 140 120 100 80 60 40 10 06287-020 frequency (hz) cmrr (db) 100 1k 10k 100k 1m g = 1 g = 2 g = 4 g = 8 figure 19. cmrr vs. frequency 120 100 140 80 60 40 10 1m 06287-021 frequency (hz) cmrr (db) 100 1k 10k 100k g = 1 g = 2 g = 4 g = 8 figure 20. cmrr vs. frequency, 1 k source imbalance ?15 ?50 130 06287-022 temperature (c) ? cmrr (v/v) 10 15 5 0 ?5 ?10 ?30 ?10 10 30 50 70 90 110 figure 21. cmrr vs. temperature, g = 1 25 ?10 1k 100m 06287-023 frequency (hz) gain (db) 10k 100k 1m 10m 20 15 10 5 0 ?5 v s = 15v v in = 200mv p-p r l = 2k ? g = 1 g = 2 g = 4 g = 8 figure 22. gain vs. frequency 40 30 20 10 ?10 ?30 0 ?20 ?40 ?10?8?6?4?20246810 06287-024 gain nonlinearity (10ppm/div) output voltage (v) figure 23. gain nonlinearity vs. output voltage, g = 1, r l = 10 k, 2 k, 600
ad8251 rev. b | page 11 of 24 40 30 20 10 ?10 ?30 0 ?20 ?40 ?10?8?6?4?20246810 06287-025 gain nonlinearity (10ppm/div) output voltage (v) figure 24. gain nonlinearity vs. output voltage, g = 2, r l = 10 k, 2 k, 600 40 30 20 10 ?10 ?30 0 ?20 ?40 ?10?8?6?4?20246810 06287-026 gain nonlinearity (10ppm/div) output voltage (v) figure 25. gain nonlinearity vs. output voltage, g = 4, r l = 10 k, 2 k, 600 40 30 20 10 ?10 ?30 0 ?20 ?40 ?10?8?6?4?20246810 06287-027 gain nonlinearity (10ppm/div) output voltage (v) figure 26. gain nonlinearity vs. output voltage, g = 8, r l = 10 k, 2 k, 600 16 ?16 ?16 16 06287-028 output voltage (v) common-mode voltage (v) 12 8 4 0 ?4 ?8 ?12 ?12 ?8 ?4 0 4 8 12 v s = 5v 0v, ?3.9v 0v, ?13.5v 0v, +13.5v ?14.2v, +7.1v ?14.2v, ?7.1v +14v, ?7v +14v, +7v ?4v, ?2v ?4v, +2.2v +4v, ?2v +4v, +2v 0v, +3.85v 0v, 15v figure 27. input common-mode voltage range vs. output voltage, g = 1 16 ?16 ?16 16 06287-029 output voltage (v) common-mode voltage (v) 12 8 4 0 ?4 ?8 ?12 ?12 ?8 ?4 0 4 8 12 v s = 5v 0v, ?3.9v 0v, ?13.5v 0v, +13.5v ?13v, +13.5v ?13v, ?13.1v +13v, +13v +13v, ?13.5v ?4v, ?3.9v ?4v, +4v +4v, ?4v +4v, +3.9v 0v, +4v v s 15v figure 28. input common-mode voltage range vs. output voltage, g = 8 35 30 25 20 15 10 5 0 ?15 ?5 ?10 5 01 0 06287-129 input bias current and offset current (na) common-mode voltage (v) 1 5 i b + i b ? i os figure 29. input bias current and offset current vs. common-mode voltage
ad8251 rev. b | page 12 of 24 + v s ?v s 41 06287-030 supply voltage (v s ) input voltage (v) referred to supply voltages 6 ?1 ?2 +2 +1 6 8 10 12 14 +125c +85c +25c ?40c +125c +85c +25c ?40c figure 30. input voltage limit vs. supply voltage, g = 1, v ref = 0 v, r l = 10 k 15 ?15 ?16 16 06287-031 differential input voltage (v) current (ma) 10 5 0 ?5 ?10 ?12 ?8 ?4 0 4 8 12 +v s fault condition (over driven input) g = 8 fault condition (over driven input) g = 8 +in ?in ?v s figure 31. fault current draw vs. input voltage, g = 8, r l = 10 k + v s ?v s 41 06287-032 supply voltage (v s ) output voltage swing (v) referred to supply voltages 6 6 8 10 12 14 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 1.0 0.8 0.6 0.4 0.2 +125c +125c + 8 5 c + 8 5 c +25c +25c ?40c ?40c figure 32. output voltage swing vs. supply voltage, g = 8, r l = 2 k + v s ?v s 41 06287-033 supply voltage (v s ) output voltage swing (v) referred to supply voltages 6 6 8 10 12 14 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 1.0 0.8 0.6 0.4 0.2 +125c +125c +85c + 2 5 c ?40c ?40c +85c + 2 5 c figure 33. output voltage swin g vs. supply voltage, g = 8, r l = 10 k 15 ?15 100 10k 06287-034 load resistance ( ? ) output voltage swing (v) 1k 10 5 0 ?5 ?10 +125c +85c +25c ?40c +125c +85c +25c ?40c figure 34. output voltage swing vs. load resistance + v s ?v s 41 06287-035 output current (ma) output voltage swing (v) referred to supply voltages 6 6 8 10 12 14 ?0.4 ?0.8 ?1.2 ?1.6 ?2.0 2.0 1.6 1.2 0.8 0.4 +125c +85c +25c ?40c +125c +85c +25c ?40c figure 35. output voltage swing vs. output current
ad8251 rev. b | page 13 of 24 2s/div 20mv/div no load 47pf 100pf 06287-036 figure 36. small signal pulse response for various capacitive loads 06287-037 5v/div 2s/div 0.002%/div 585ns to 0.01% 723ns to 0.001% figure 37. large signal pulse response and settling time, g = 1, r l = 10 k 06287-038 5v/div 2s/div 0.002%/div 400ns to 0.01% 600ns to 0.001% figure 38. large signal pulse response and settling time, g = 2, r l = 10 k 06287-039 5v/div 2s/div 0.002%/div 376ns to 0.01% 640ns to 0.001% figure 39. large signal pulse response and settling time, g = 4, r l = 10 k 06287-040 5v/div 2s/div 0.002%/div 364ns to 0.01% 522ns to 0.001% figure 40. large signal pulse response and settling time, g = 8, r l = 10 k 06287-041 25mv/div 2s/div figure 41. small signal response, g = 1, r l = 2 k, c l = 100 pf
ad8251 rev. b | page 14 of 24 06287-042 25mv/div 2s/div figure 42. small signal response, g = 2, r l = 2 k, c l = 100 pf 06287-043 25mv/div 2s/div figure 43. small signal response, g = 4, r l = 2 k, c l = 100 pf 06287-044 25mv/div 2s/div figure 44. small signal response, g = 8, r l = 2 k, c l = 100 pf 06287-045 1200 0 22 step size (v) time (ns) 0 1000 800 600 400 200 4 6 8 1012141618 settled to 0.01% settled to 0.001% figure 45. settling time vs. step size, g = 1, r l = 10 k 06287-046 1200 0 22 step size (v) time (ns) 0 1000 800 600 400 200 4 6 8 1012141618 settled to 0.01% settled to 0.001% figure 46. settling time vs. step size, g = 2, r l = 10 k 06287-047 1200 0 22 step size (v) time (ns) 0 1000 800 600 400 200 4 6 8 1012141618 settled to 0.01% settled to 0.001% figure 47. settling time vs. step size, g = 4, r l = 10 k
ad8251 rev. b | page 15 of 24 06287-048 1200 0 22 step size (v) time (ns) 0 ? 50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?120 ?115 ?110 ?105 ?100 10 1m 06287-050 frequency (hz) thd + n (db) 100 1k 10k 100k g = 2 g = 4 g = 8 g = 1 1000 800 600 400 200 4 6 8 1012141618 settled to 0.01% settled to 0.001% figure 48. settling time vs. step size, g = 8, r l = 10 k figure 50. total harmonic distortion + noise vs. frequency, 10 hz to 500 khz band-pass filter, r l = 2 k ? 50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?120 ?115 ?110 ?105 ?100 10 1m 06287-049 frequency (hz) thd + n (db) 100 1k 10k 100k g = 8 g = 2 g = 1 g = 4 figure 49. total harmonic distortion + noise vs. frequency, 10 hz to 22 khz band-pass filter, r l = 2 k
ad8251 rev. b | page 16 of 24 theory of operation 10k ? 10k ? 10k ? 10k ? ref out a3 ? in +in wr 2.2k ? 2.2k ? + v s + v s ?v s ?v s +v s ?v s +v s ?v s a1 a0 2.2k ? dgnd a1 a2 digital gain control 2.2k ? +v s ?v s +v s ?v s +v s ?v s +v s ?v s 0 6287-061 figure 51. simplified schematic the ad8251 is a monolithic instrumentation amplifier based on the classic 3-op-amp topology, as shown in figure 51 . it is fabricated on the analog devices, inc., proprietary i cmos? process that provides precision, linear performance, and a robust digital interface. a parallel interface allows users to digitally program gains of 1, 2, 4, and 8. gain control is achieved by switching resistors in an internal, precision resistor array (as shown in figure 51 ). although the ad8251 has a voltage feedback topology, the gain bandwidth product increases for gains of 1, 2, and 4 because each gain has its own frequency compensation. this results in maximum bandwidth at higher gains. all internal amplifiers employ distortion cancellation circuitry and achieve high linearity and ultralow thd. laser trimmed resistors allow for a maximum gain error of less than 0.03% for g = 1 and minimum cmrr of 98 db for g = 8. a pinout optimized for high cmrr over frequency enables the ad8251 to offer a guaranteed minimum cmrr over frequency of 80 db at 50 khz (g = 1). the balanced input reduces the parasitics that, in the past, adversely affected cmrr performance. gain selection logic low and logic high voltage limits are listed in the specifications section. typically, logic low is 0 v and logic high is 5 v; both voltages are measured with respect to dgnd. see table 2 for the permissible voltage range of dgnd. the gain of the ad8251 can be set using two methods. transparent gain mode the easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to a0 and a1. figure 52 shows an example of this gain setting method, referred to through- out the data sheet as transparent gain mode. tie wr to the negative supply to engage transparent gain mode. in this mode, any change in voltage applied to a0 and a1 from logic low to logic high, or vice versa, immediately results in a gain change. is the truth table for transparent gain mode, and shows the ad8251 configured in transparent gain mode. table 5 figure 52 +15 v ?15v ?15v a0 a1 wr +in +5v +5v ?in 10 f0.1f 10 f0.1f g = 8 dgnd dgnd ref ad8251 note: 1. in transparent gain mode, wr is tied to ? v s . the voltage levels on a0 and a1 determine the gain. in this example, both a0 and a1 are set to logic high, resulting in a gain of 8. 0 6287-051 figure 52. transparent gain mode, a0 and a1 = high, g = 8
ad8251 rev. b | page 17 of 24 table 5. truth table logic levels for transparent gain mode wr a1 a0 gain ?v s low low 1 ?v s low high 2 ?v s high low 4 ?v s high high 8 latched gain mode some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same pcb. in such cases, devices can share a data bus. the gain of the ad8251 can be set using wr as a latch, allowing other devices to share a0 and a1. shows a schematic using this method, known as latched gain mode. the ad8251 is in this mode when figure 53 wr is held at logic high or logic low, typically 5 v and 0 v, respectively. the voltages on a0 and a1 are read on the downward edge of the wr signal as it transitions from logic high to logic low. this latches in the logic levels on a0 and a1, resulting in a gain change. see the truth table in for more information on these gain changes. table 6 +15 v ?15v a0 a1 wr +in ?in 10 f0.1f 10 f0.1f dgnd dgnd ref ad8251 a0 a1 wr +5v +5v +5v 0v 0v 0v g = previous state g = 8 + ? note: 1. on the downward edge of wr, as it transitions from logic high to logic low, the voltages on a0 and a1 are read and latched in, resulting in a gain change. in this example, the gain switches to g = 8. 06287-052 figure 53. latched gain mode, g = 8 table 6. truth table logic le vels for latched gain mode wr a1 a0 gain high to low low low change to 1 high to low low high change to 2 high to low high low change to 4 high to low high high change to 8 low to low x 1 x 1 no change low to high x 1 x 1 no change high to high x 1 x 1 no change 1 x = dont care. on power-up, the ad8251 defaults to a gain of 1 when in latched gain mode. in contrast, if the ad8251 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on a0 and a1 at power-up. timing for latched gain mode in latched gain mode, logic levels at a0 and a1 must be held for a minimum setup time, t su , before the downward edge of wr latches in the gain. similarly, they must be held for a minimum hold time of t hd after the downward edge of wr to ensure that the gain is latched in correctly. after t hd , a0 and a1 can change logic levels, but the gain does not change (until the next downward edge of wr ). the minimum duration that wr can be held high is t wr -high , and the minimum duration that wr can be held low is t wr -low . digital timing specifications are listed in the time required for a gain change is dominated by the settling time of the amplifier. a timing diagram is shown in . table 2. figure 54 when sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the ad8251. feedthrough can be minimized by decreasing the edge rate of the logic signals. furthermore, careful layout of the pcb also reduces coupling between the digital and analog portions of the board. pull-up or pull-down resistors should be used to provide a well-defined voltage at the a0 and a1 pins. a0, a1 wr t su t hd t wr-high t wr-low 0 6287-053 figure 54. timing diagram for latched gain mode
ad8251 rev. b | page 18 of 24 power supply regulation and bypassing the ad8251 has high psrr. however, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. noise on the supply pins can adversely affect per- formance. as in all linear circuits, bypass capacitors must be used to decouple the amplifier. place a 0.1 f capacitor close to each supply pin. a 10 f tantalum capacitor can be used farther away from the part (see figure 55 ) and, in most cases, it can be shared by other precision integrated circuits. ad8251 + v s +in ?in load ref 0.1f 10f 0.1f 10f ?v s dgnd out dgnd a0 a1 wr 06287-054 figure 55. supply decoupling, ref, and output referred to ground input bias current return path the ad8251 input bias current must have a return path to its local analog ground. when the source, such as a thermocouple, cannot provide a return current path, one should be created (see figure 56 ). thermocouple +v s ref ?v s ad8251 capacitively coupled +v s ref c c ?v s ad8251 transformer +v s ref ?v s ad8251 incorrect capacitively coupled +v s ref c r r c ?v s ad8251 1 f high-pass = 2 rc thermocouple +v s ref ?v s 10m ? ad8251 transformer +v s ref ?v s ad8251 correct 06287-055 figure 56. creating an i bias return path input protection all terminals of the ad8251 are protected against esd. note that 2.2 k series resistors precede the esd diodes as shown in figure 51 . the resistors limit current into the diodes and allow for dc overload conditions 13 v above the positive supply and 13 v below the negative supply. an external resistor should be used in series with each input to limit current for voltages greater than 13 v beyond either supply rail. in either scenario, the ad8251 safely handles a continuous 6 ma current at room temperature. for applications where the ad8251 encounters extreme overload voltages, external series resistors and low leakage diode clamps, such as bav199ls, fjh1100s, or sp720s, should be used.
ad8251 rev. b | page 19 of 24 reference terminal the reference terminal, ref, is at one end of a 10 k resistor (see figure 51 ). the instrumentation amplifier output is referenced to the voltage on the ref terminal; this is useful when the output signal needs to be offset to voltages other than its local analog ground. for example, a voltage source can be tied to the ref pin to level shift the output so that the ad8251 can interface with a single-supply adc. the allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. the ref pin should not exceed either +v s or ?v s by more than 0.5 v. for best performance, especially in cases where the output is not measured with respect to the ref terminal, source imped- ance to the ref terminal should be kept low because parasitic resistance can adversely affect cmrr and gain accuracy. incorrect ad8251 v ref correct ad8251 op1177 + ? v ref 0 6287-056 figure 57. driving the reference pin common-mode input voltage range the 3-op-amp architecture of the ad8251 applies gain and then removes the common-mode voltage. therefore, internal nodes in the ad8251 experience a combination of both the gained signal and the common-mode signal. this combined signal can be limited by the voltage supplies even when the individual input and output signals are not. figure 27 and figure 28 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains. layout grounding in mixed-signal circuits, low level analog signals need to be isolated from the noisy digital environment. designing with the ad8251 is no exception. its supply voltages are referenced to an analog ground. its digital circuit is referenced to a digital ground. although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and pcb can cause errors. therefore, use separate analog and digital ground planes. analog and digital ground should meet at one point only: star ground. the output voltage of the ad8251 develops with respect to the potential on the reference terminal. take care to tie ref to the appropriate local analog ground or to connect it to a voltage that is referenced to the local analog ground. coupling noise t o prevent coupling noise onto the ad8251, follow these guidelines: ? do not run digital lines under the device. ? run the analog ground plane under the ad8251. ? shield fast switching signals with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. ? avoid crossover of digital and analog signals. ? connect digital and analog ground at one point only (typically under the adc). ? use large traces on the power supply lines to ensure a low impedance path. decoupling is necessary; follow the guidelines listed in the power supply regulation and bypassing section. common-mode rejection the ad8251 has high cmrr over frequency, giving it greater immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical instrumentation amplifiers whose cmrr falls off around 200 hz. the typical instrumentation amplifiers often need common-mode filters at their inputs to compensate for this shortcoming. the ad8251 is able to reject cmrr over a greater frequency range, reducing the need for input common-mode filtering. careful board layout maximizes system performance. to maintain high cmrr over frequency, lay out the input traces symmetrically. ensure that the traces maintain resistive and capacitive balance; this holds for additional pcb metal layers under the input pins and traces. source resistance and capaci- tance should be placed as close to the inputs as possible. should a trace cross the inputs (from another layer), it should be routed perpendicular to the input traces.
ad8251 rev. b | page 20 of 24 rf interference driving an adc rf rectification is often a problem when amplifiers are used in applications where there are strong rf signals. the disturbance can appear as a small dc offset voltage. high frequency signals can be filtered with a low-pass rc network placed at the input of the instrumentation amplifier, as shown in figure 58 . the filter limits the input signal bandwidth according to the following relationship: an instrumentation amplifier is often used in front of an adc to provide cmrr. usually, instrumentation amplifiers require a buffer to drive an adc. however, the low output noise, low distortion, and low settle time of the ad8251 make it an excellent adc driver. in figure 59 , a 1 nf capacitor and a 49.9 resistor create an antialiasing filter for the ad7612 . the 1 nf capacitor stores and delivers the necessary charge to the switched capacitor input of the adc. the 49.9 series resistor reduces the burden of the 1 nf load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the ad7612 . selecting too small a resistor improves the correlation between the voltage at the output of the ad8251 and the voltage at the input of the ad7612 but may destabilize the ad8251. a trade- off must be made between selecting a resistor small enough to maintain accuracy and large enough to maintain stability. )cc(r 1 filterfreq c d diff + = 22 c cm rc 1 filterfreq 2 = where c d 10 c c . r r ad8251 +15 v +in ?in 0.1f 10f 10f 0.1f ref v out ?15v c d c c c c 0 6287-057 0.1 f 0.1 f 1nf 49.9 ? ad7612 adr435 +12v ?12v +5v +15 v ?15v a0 a1 wr +in ? in 10 f0.1f 10 f0.1f ref ad8251 dgnd dgnd 06287-058 figure 58. rfi suppression va lu e s of r a nd c c should be chosen to minimize rfi. a mismatch between the r c c at the positive input and the r c c at negative input degrades the cmrr of the ad8251. by using a value of c d that is 10 times larger than the value of c figure 59. driving an adc c , the effect of the mismatch is reduced and performance is improved.
ad8251 rev. b | page 21 of 24 applications differential output in certain applications, it is necessary to create a differential signal. high resolution adcs often require a differential input. in other cases, transmission over a long distance can require differential signals for better immunity to interference. figure 61 shows how to configure the ad8251 to output a differential signal. an op amp, the ad817 , is used in an inverting topology to create a differential voltage. v ref sets the output midpoint according to the equation shown in the figure. errors from the op amp are common to both outputs and are thus common mode. likewise, errors from using mismatched resistors cause a common-mode dc offset error. such errors are rejected in differential signal processing by differential input adcs or instrumentation amplifiers. when using this circuit to drive a differential adc, v ref can be set using a resistor divider from the adc reference to make the output ratiometric with the adc. setting gains with a microcontroller +15 v micro- controller ?15v a0 a1 wr +in ? in 10 f0.1f 10 f0.1f ref ad8251 + ? dgnd dgnd 06287-059 figure 60. programming gain using a microcontroller +12 v ?12v a0 a1 wr +in 10 f 0.1 f 10 f 0.1 f ad8251 ref g = 1 0.1f 4.99k ? 4.99k ? ad817 0.1f +12v ?12v v ref 0v v out a = v in + v ref 2 2 v out b = ?v in + v ref +2.5v ?2.5v 0v +2.5v ?2.5v 0v time amplitude 0v time amplitude +5 v ?5v amplitude 10pf +12v ?12v v in + ? +? dgnd dgnd 06287-060 figure 61. differential output with level shift
ad8251 rev. b | page 22 of 24 data acquisition the ad8251 makes an excellent instrumentation amplifier for use in data acquisition systems. its wide bandwidth, low distortion, low settling time, and low noise enable it to condition signals in front of a variety of 16-bit adcs. figure 63 shows a schematic of the ad825x data acquisition demonstration board. the quick slew rate of the ad8251 allows it to condition rapidly changing signals from the multiplexed inputs. an fpga controls the ad7612 , ad8251, and adg1209 . in addition, mechanical switches and jumpers allow users to pin strap the gains when in transparent gain mode. this system achieved ?106 db of thd at 1 khz and a signal-to- noise ratio of 91 db during testing, as shown in figure 62 . ? 70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 ?180 05 06287-062 frequency (khz) amplitude (db) 0 5 1015202530354045 figure 62. fft of the ad 825x daq demo board using the ad8251 1 khz signal ad8251 2 +in ?in a1 a0 out ref ?v s +v s dgnd 5 3 4 9 1 7 10 11 12 13 14 15 16 6 2 s1a en s2a s3a s4a da db gnd s1b s2b s3b s4b a0 a1 v ss v dd jmp jmp jmp +12v ?12v +12v ?12v jmp jmp ?v s +5v +5v dgnd 806 ? 806 ? 806 ? 806 ? 806 ? 806 ? 806 ? 806 ? 0 ? 0 ? 49.9 ? 0 ? ?ch1 +ch1 +ch2 ?ch2 +ch3 ?ch3 +ch4 ?ch4 1nf 2k ? 2k ? 0.1f gnd +12v ?12v + + 10f 10f 0.1f c d c c c c c3 0.1f c4 0.1f +5v +5v dgnd dgnd r8 2k ? +in ad7612 adr435 adg1209 dgnd altera epf6010atc144-3 8 0 ? 0 ? 1 10 6 wr 9 4 5 8 3 7 + ? dgnd 2k ? dgnd 06287-067 figure 63. schematic of adg1209 , ad8251, and ad7612 in the ad825x daq demo board
ad8251 rev. b | page 23 of 24 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 64. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ad8251armz ?40c to +85c 10-lead mini small outline package [msop] rm-10 h0t ad8251armz-rl ?40c to +85c 10-lead mini small outline package [msop] rm-10 h0t ad8251armz-r7 ?40c to +85c 10-lead mini small outline package [msop] rm-10 h0t AD8251-EVALZ evaluation board 1 z = rohs compliant part.
ad8251 rev. b | page 24 of 24 notes ?2007C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06287-0-11/10(b)

▲Up To Search▲

Price & Availability of AD8251-EVALZ

	To Download AD8251-EVALZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .